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Joined 1 year ago
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Cake day: August 23rd, 2023

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  • @T4V0 I use Notepad to write scripts.I don’t think it works that way with the code written like this

    **library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    entity tb_Kitchen_Timer is
    end tb_Kitchen_Timer;
    architecture tb of tb_Kitchen_Timer is
    signal clk : std_logic := ‘0’;
    signal reset : std_logic := ‘0’;
    signal start : std_logic := ‘0’;
    signal stop : std_logic := ‘0’;
    signal adjust_interval_up : std_logic := ‘0’;
    signal adjust_interval_down : std_logic := ‘0’;
    signal alarm : std_logic;
    constant TbPeriod : time := 10 ns;
    signal TbClock : std_logic := ‘0’;
    signal TbSimEnded : std_logic := ‘0’;
    begin
    dut : entity work.Kitchen_Timer
    port map
    (
    clk => clk,
    reset => reset,
    start => start,
    stop => stop,
    adjust_interval_up => adjust_interval_up,
    adjust_interval_down => adjust_interval_down,
    alarm => alarm
    )
    TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= ‘1’ else ‘0’; – Clock generation
    clk <= TbClock;
    stimuli : process
    variable num_ticks : natural;
    begin
    -- Reset generation
    reset <= ‘1’;
    wait for 20 ns;
    reset <= ‘0’;
    wait for 20 ns;
    -- Start the timer
    start <= ‘1’;
    wait for 20 ns;
    start <= ‘0’;
    stop <= ‘1’;
    -- Adjust interval up and down
    adjust_interval_up <= ‘1’;
    wait for 10 ns;
    start <= ‘1’;
    stop <= ‘0’;
    adjust_interval_up <= ‘0’;
    wait for 30 ns;
    start <= ‘0’;
    stop <= ‘1’;
    adjust_interval_down <= ‘1’;
    wait for 10 ns;
    start <= ‘1’;
    stop <= ‘0’;
    adjust_interval_down <= ‘0’;
    wait for 20 ns;
    start <= ‘0’;
    stop <= ‘1’;
    adjust_interval_up <= ‘1’;
    wait for 600 ns;
    start <= ‘1’;
    stop <= ‘0’;
    adjust_interval_up <= ‘0’;
    -- Wait for the timer to reach the alarm interval (60 clocks)
    wait for 600 ns; – Simulate for the required time
    -- Stop the timer
    start <= ‘0’;
    stop <= ‘1’;
    wait for 100 ns;
    -- Stop the clock and terminate the simulation
    TbSimEnded <= ‘1’;
    wait;
    end process;
    end tb;
    **







  • @T4V0 Do you understand Proteus?
    I have an error in my schematic, and I can’t figure out what it is
    Design the internal block diagram of the Timer 555 circuit. Using the designed circuit
    make a pulse width modulated (PWM) amplifier. The amplifier works by
    at the output it generates a pulse-width modulated signal of a frequency much higher than
    frequency of the signal being amplified and often the frequency of the generated signal is 60
    kilohertz if it is an audio amplifier. Depending on the intensity of the input signal,
    the mean value of the generated signal at the output changes. By using
    of the low-pass filter, a signal is obtained which is an amplified version of the input.
    The functionality of the amplifier can be demonstrated by applying a sinusoidal signal at the input

    And this is whole diagram of project:




  • @T4V0 I just now see your messages, thank you…
    In the meantime, I made something like this…
    What do you think about the specifications that the project requires, should I stick to your code or should I add something from my own code?
    Does your simulation correspond to a time of 1 hour and should there be alarming on the simulation?

    Vhdl code:

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    entity Kitchen_Timer is
    port (
    clk : in std_logic; – Clock input
    reset : in std_logic; – Reset input
    start : in std_logic; – Start button input
    stop : in std_logic; – Stop button input
    adjust_interval_up : in std_logic; – Button for increasing alarm interval
    adjust_interval_down : in std_logic; – Button for decreasing alarm interval
    alarm : out std_logic – Alarm output
    );
    end entity Kitchen_Timer;
    architecture Behavioral of Kitchen_Timer is
    signal count : integer range 0 to 3600000 := 0; – Adjust range for 1 hour
    signal alarming : std_logic := ‘0’;
    signal alarm_interval : integer range 600 to 3600000 := 600; – Adjust range for 1 hour
    begin
    process (clk, reset)
    begin
    if reset = ‘1’ then
    count <= 0;
    alarm_interval <= 600;
    elsif rising_edge(clk) then
    if start = ‘1’ then
    count <= count + 1;
    end if;
    if stop = ‘1’ or count = alarm_interval then
    count <= 0;
    end if;
    if adjust_interval_up = ‘1’ then
    if alarm_interval < 3600000 then
    alarm_interval <= alarm_interval + 600; – Adjust increment for 1 minute
    end if;
    count <= 0; – Reset count when adjusting interval
    elsif adjust_interval_down = ‘1’ then
    if alarm_interval > 600 then
    alarm_interval <= alarm_interval - 600; – Adjust decrement for 1 minute
    end if;
    count <= 0; – Reset count when adjusting interval
    end if;
    end if;
    end process;
    alarming <= ‘1’ when count >= alarm_interval else ‘0’;
    alarm <= alarming;
    end architecture Behavioral;

    Testbench:

    library ieee;
    use ieee.std_logic_1164.all;
    entity tb_Kitchen_Timer is
    end tb_Kitchen_Timer;
    architecture tb of tb_Kitchen_Timer is
    component Kitchen_Timer
    port (
    clk : in std_logic;
    reset : in std_logic;
    start : in std_logic;
    stop : in std_logic;
    adjust_interval_up : in std_logic;
    adjust_interval_down : in std_logic;
    alarm : out std_logic
    );
    end component;
    signal clk : std_logic := ‘0’;
    signal reset : std_logic := ‘0’;
    signal start : std_logic := ‘0’;
    signal stop : std_logic := ‘0’;
    signal adjust_interval_up : std_logic := ‘0’;
    signal adjust_interval_down : std_logic := ‘0’;
    signal alarm : std_logic;
    constant TbPeriod : time := 20 ns;
    signal TbClock : std_logic := ‘0’;
    signal TbSimEnded : std_logic := ‘0’;
    begin
    dut : Kitchen_Timer
    port map (
    clk => clk,
    reset => reset,
    start => start,
    stop => stop,
    adjust_interval_up => adjust_interval_up,
    adjust_interval_down => adjust_interval_down,
    alarm => alarm
    );
    -- Clock generation
    TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= ‘1’ else ‘0’;
    clk <= TbClock;
    stimuli : process
    variable num_ticks : natural;
    begin
    -- Reset generation
    reset <= ‘1’;
    wait for 200 us;
    reset <= ‘0’;
    wait for 200 us;
    -- Start the timer
    start <= ‘1’;
    wait for 500 us;
    -- Adjust interval up and down
    adjust_interval_up <= ‘1’;
    wait for 100 us;
    adjust_interval_up <= ‘0’;
    wait for 100 us;
    adjust_interval_down <= ‘1’;
    wait for 100 us;
    adjust_interval_down <= ‘0’;
    wait for 100 us;
    -- Wait for the timer to reach the alarm interval (3600000 clocks)
    wait for 72 ms; – Simulate for the required time
    -- Stop the timer
    start <= ‘0’;
    wait for 300 us;
    -- Stop the clock and terminate the simulation
    TbSimEnded <= ‘1’;
    wait;
    end process;
    end tb;


  • @T4V0 I
    In the meantime, I worked on improving the code.

    VHDL code:
    llibrary ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    entity Kitchen_Timer is
    port (
    clk : in std_logic; – Clock input
    reset : in std_logic; – Reset input
    start : in std_logic; – Start button input
    stop : in std_logic; – Stop button input
    adjust_interval_up : in std_logic; – Button for increasing alarm interval
    adjust_interval_down : in std_logic; – Button for decreasing alarm interval
    alarm : out std_logic – Alarm output
    );
    end entity Kitchen_Timer;
    architecture Behavioral of Kitchen_Timer is
    signal count : integer range 0 to 3600000 := 0; – Adjust range for 1 hour
    signal alarming : std_logic := ‘0’;
    signal alarm_interval : integer range 600 to 3600000 := 600; – Adjust range for 1 hour
    begin
    process (clk, reset)
    begin
    if reset = ‘1’ then
    count <= 0;
    alarm_interval <= 600;
    elsif rising_edge(clk) then
    if start = ‘1’ then
    count <= count + 1;
    end if;
    if stop = ‘1’ or count = alarm_interval then
    count <= 0;
    end if;
    if adjust_interval_up = ‘1’ then
    if alarm_interval < 3600000 then
    alarm_interval <= alarm_interval + 600; – Adjust increment for 1 minute
    end if;
    count <= 0; – Reset count when adjusting interval
    elsif adjust_interval_down = ‘1’ then
    if alarm_interval > 600 then
    alarm_interval <= alarm_interval - 600; – Adjust decrement for 1 minute
    end if;
    count <= 0; – Reset count when adjusting interval
    end if;
    end if;
    end process;
    alarming <= ‘1’ when count >= alarm_interval else ‘0’;
    alarm <= alarming;
    end architecture Behavioral;

    Testbench:

    library ieee;
    use ieee.std_logic_1164.all;

    entity tb_Kitchen_Timer is
    end tb_Kitchen_Timer;
    architecture tb of tb_Kitchen_Timer is
    component Kitchen_Timer
    port (
    clk : in std_logic;
    reset : in std_logic;
    start : in std_logic;
    stop : in std_logic;
    adjust_interval_up : in std_logic;
    adjust_interval_down : in std_logic;
    alarm : out std_logic
    );
    end component;
    signal clk : std_logic := ‘0’;
    signal reset : std_logic := ‘0’;
    signal start : std_logic := ‘0’;
    signal stop : std_logic := ‘0’;
    signal adjust_interval_up : std_logic := ‘0’;
    signal adjust_interval_down : std_logic := ‘0’;
    signal alarm : std_logic;
    constant TbPeriod : time := 20 ns;
    signal TbClock : std_logic := ‘0’;
    signal TbSimEnded : std_logic := ‘0’;
    begin
    dut : Kitchen_Timer
    port map (
    clk => clk,
    reset => reset,
    start => start,
    stop => stop,
    adjust_interval_up => adjust_interval_up,
    adjust_interval_down => adjust_interval_down,
    alarm => alarm
    );
    -- Clock generation
    TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= ‘1’ else ‘0’;
    clk <= TbClock;
    stimuli : process
    variable num_ticks : natural;
    begin
    -- Reset generation
    reset <= ‘1’;
    wait for 200 us;
    reset <= ‘0’;
    wait for 200 us;
    -- Start the timer
    start <= ‘1’;
    wait for 500 us;
    -- Adjust interval up and down
    adjust_interval_up <= ‘1’;
    wait for 100 us;
    adjust_interval_up <= ‘0’;
    wait for 100 us;
    adjust_interval_down <= ‘1’;
    wait for 100 us;
    adjust_interval_down <= ‘0’;
    wait for 100 us;
    -- Wait for the timer to reach the alarm interval (3600000 clocks)
    wait for 72 ms; – Simulate for the required time
    -- Stop the timer
    start <= ‘0’;
    wait for 300 us;
    -- Stop the clock and terminate the simulation
    TbSimEnded <= ‘1’;
    wait;
    end process;
    end tb;

    And this is simulation:


  • @T4V0 Hello, I’ve been doing a lot of research on this project these days and I’ve brought the code to a better level, I hope… But I’m not sure if this simulation…

    This is VHDL code:
    library ieee;

    use ieee.std_logic_1164.all;

    use ieee.numeric_std.all;

    entity Kitchen_Timer is

    port (

    clk : in std_logic; – Clock input

    reset : in std_logic; – Reset input

    start : in std_logic; – Start button input

    stop : in std_logic; – Stop button input

    adjust_interval_up : in std_logic; – Button for increasing alarm interval

    adjust_interval_down : in std_logic; – Button for decreasing alarm interval

    alarm : out std_logic – Alarm output

    );

    end entity Kitchen_Timer;

    architecture Behavioral of Kitchen_Timer is

    signal count : integer range 0 to 3600000 := 0; – Adjust range for 1 hour

    signal alarming : std_logic := ‘0’;

    signal alarm_interval : integer range 600 to 3600000 := 600; – Adjust range for 1 hour

    begin

    process (clk, reset)

    begin

    if reset = ‘1’ then

    count <= 0;

    alarming <= ‘0’;

    alarm_interval <= 600;

    elsif rising_edge(clk) then

    if start = ‘1’ then

    count <= count + 1;

    end if;

    if stop = ‘1’ or count = alarm_interval then

    count <= 0;

    end if;

    if adjust_interval_up = ‘1’ then

    if alarm_interval < 3600000 then

    alarm_interval <= alarm_interval + 600; – Adjust increment for 1 minute

    end if;

    elsif adjust_interval_down = ‘1’ then

    if alarm_interval > 600 then

    alarm_interval <= alarm_interval - 600; – Adjust decrement for 1 minute

    end if;

    end if;

    end if;

    end process;

    alarming <= ‘1’ when count >= alarm_interval else ‘0’;

    alarm <= alarming;

    end architecture Behavioral;

    This is Testbench:
    library ieee;

    use ieee.std_logic_1164.all;

    entity tb_Kitchen_Timer is

    end tb_Kitchen_Timer;

    architecture tb of tb_Kitchen_Timer is

    component Kitchen_Timer

    port (

    clk : in std_logic;

    reset : in std_logic;

    start : in std_logic;

    stop : in std_logic;

    adjust_interval_up : in std_logic;

    adjust_interval_down : in std_logic;

    alarm : out std_logic

    );

    end component;

    signal clk : std_logic := ‘0’;

    signal reset : std_logic := ‘0’;

    signal start : std_logic := ‘0’;

    signal stop : std_logic := ‘0’;

    signal adjust_interval_up : std_logic := ‘0’;

    signal adjust_interval_down : std_logic := ‘0’;

    signal alarm : std_logic;

    constant TbPeriod : time := 1 us; – Set the clock period to 1us

    signal TbClock : std_logic := ‘0’;

    signal TbSimEnded : std_logic := ‘0’;

    begin

    dut : Kitchen_Timer

    port map (

    clk => clk,

    reset => reset,

    start => start,

    stop => stop,

    adjust_interval_up => adjust_interval_up,

    adjust_interval_down => adjust_interval_down,

    alarm => alarm

    );

    -- Clock generation

    TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= ‘1’ else ‘0’;

    clk <= TbClock;

    stimuli : process

    begin

    -- Reset generation

    reset <= ‘1’;

    wait for 20 us; – Adjust delay to fit the new clock period

    reset <= ‘0’;

    -- Add your stimuli and test cases here

    -- For example:

    start <= ‘1’;

    wait for 50 us; – Adjust delay to fit the new clock period

    start <= ‘0’;

    wait for 400 us; – Adjust delay to fit the new clock period

    adjust_interval_up <= ‘1’;

    wait for 20 us; – Adjust delay to fit the new clock period

    adjust_interval_up <= ‘0’;

    wait for 50 us; – Adjust delay to fit the new clock period

    adjust_interval_down <= ‘1’;

    wait for 20 us; – Adjust delay to fit the new clock period

    adjust_interval_down <= ‘0’;

    wait for 50 us; – Adjust delay to fit the new clock period

    -- …

    -- Stop the clock and hence terminate the simulation

    TbSimEnded <= ‘1’;

    wait;

    end process;

    end tb;

    -- Configuration block below is required by some simulators. Usually no need to edit.

    configuration cfg_tb_Kitchen_Timer of tb_Kitchen_Timer is

    for tb

    end for;

    end cfg_tb_Kitchen_Timer;
    And this is result of simulation: